1. Field of the Invention
The present invention generally relates to a semiconductor device, and a manufacturing method thereof, and especially relates to a method of evaluating impurities distribution of a silicon active region under a gate electrode, and a semiconductor device and its manufacturing method suitable for evaluation of such impurities distribution.
2. Description of the Related Art
With the “ubiquitous era” arriving, information apparatuses are required to be even more miniaturized, capable of providing even higher performance, and capable of operating with even less power. Detailed ruling (design rule) for LSIs used in, e.g., servers, digital household electric appliances, and cellular phones, is progressing. Developments of “45 nm-generation” transistors are advancing, wherein the line width of a gate electrode is less than 40 nm. For stable operations of LSIs that contain a great number of such detailed-ruling transistors, it is important that the performance of each transistor be uniform, so that a transistor manufacturing method that reduces variations in the performance becomes important.
If variations by etching to shape the form of gate electrodes of transistors are great, variations of operating characteristics of the transistors are great. Accordingly, for determining a cause of the variations of the transistor performance, a method of evaluating the processed form after etching the gate electrodes (gate LER, Gate Line Edge Roughness) by an electron microscope is widely used during manufacturing.
However, a variation of the processed form of the gate electrode observed by the electron microscope is not necessarily the same as the variation of the transistor performance. That is, even if the degree of the variation of the processed form of the gate electrode is the same as that of a transistor, the variations of the performance may differ from transistor to transistor. This is because of variation of impurities distribution at a boundary between a channel region and an extension region of the source-drain diffusion layer extending to a silicon active region under the gate electrode.
Accordingly, it is conceivable to directly measure and evaluate the impurities distribution in the active region with a scanning tunneling microscope (STM) by removing the gate electrode.
FIG. 1 shows an example wherein a conventional etching method is applied to the gate electrode removal for visually inspecting impurities distribution. On the left side of FIG. 1, at (a), a sidewall insulating film 106 is formed on a side wall of a poly silicon gate electrode 105 that is formed on a silicon substrate 101 through a gate insulating film (gate oxide film) 104. Further, a source electrode 102 and a drain electrode 102 are formed on the silicon substrate 101, with a channel 103 in between. As described above, an extension overlap distance (D) of the source electrode and the drain electrode 102 projecting to the silicon active region directly under the gate electrode 105 is one of important parameters for estimating transistor characteristics. In order to obtain the extension overlap distance (D), measurement and evaluation of the impurities distribution are required.
Conventionally, wet etching by KOH, hydrofluoric acid-nitric acid (HF—HNO3), organic alkali, and the like is performed for removing the gate electrode 105, which is made of poly silicon, and an etching selectivity of the poly silicon to a gate insulating film is taken. However, since precise adjustment of the mixing ratio and process temperature is difficult, the gate insulating film 104 and the active region thereunder are often removed as shown on the right of FIG. 1 at (b). That is, a damage section 108 is generated in the substrate silicon, and consequently, it is impossible to correctly measure the impurities distribution.
In the case of the technology of less than 0.13 μm, the performance degradation due to depletion of gate electrodes of MOSFETs is serious, and attempts are made wherein metal is used for the gate electrode. In this case, it is difficult to manufacture MOSFETs by the same technique as the conventional poly silicon gate. As a result, the technology called the replacement gate or damascene gate is widely used. According to the replacement gate method, a typical manufacturing process is as follows: a source and a drain are formed using a dummy polysilicon; an insulator layer is covered; the gate surface is appeared by a CMP (Chemical-Mechanical Polishing) method; the dummy gate is selectively etched; and then a gate insulation film and a metal gate electrode are formed.
In the manufacturing process as described above (the replacement gate), the same problem of seriously damaging a channel layer arises, because the gate insulating film is also removed when selectively removing the dummy gate. As described above, it is difficult to obtain a satisfactory etching selectivity with the conventional wet process, and the substrate silicon is often damaged. Although there have been attempts to solve the problem by structuring the dummy gate with three layers of Poly/SiN/SiO2, this increases the number of manufacturing steps, which is not desirable.
Further, in order to solve the problem, another method of removing only the gate electrode 105 made of poly silicon without melting the gate insulating film 104 is proposed, wherein a solution of TMAH (tetrapod methyl ammonium hydro-oxide) is used and conditions of a TMAH process are optimized (for example, Non-Patent Reference 1).
[Non-Patent Reference 1] H. Fukutomo, et al., “Direct evaluation of Gate Line Roughness Impact on Extension Profiles in Sub-50 nm N-MOSFETs”, IEDM Tech. Dig., pp. 433-436, December 2004.